IMX93CEC datasheet(26/123 Pages) NXP

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POR_B

NVCC_SD2

(0.6 V LPDDR4X)

VDDQ_DDR

VDD2_DDR

VDD_ANA_0P8, VDD_

VDD_SOC

PMIC_ON_REQ

NVCC_BBSM_1P8

NVCC_XXX_3P3

VDD_USB_3P3

VDDQ_DDR (1.1 V LPDDR4)

VDD_ANAx_1P8,

VDD_MIPI_1P8,

VDD_LVDS_1P8,

NVCC_XXX(1P8)

VDD_USB_1P8,

MIPI_0P8, VDD_USB_0P8

BBSM

Figure 4. The power sequence of i.MX 93 processors

Note: POR_B must be asserted whenever VDD_SOC is powered down, but NVCC_BBSM_1P8 is powered up (when the

processor is in BBSM mode).

4.3.1 Power-up sequence

The power-up sequence of i.MX 93 is defined as follows:

1. Turn on NVCC_BBSM_1P8

2. [The SoC will assert PMIC_ON_REQ at this point in time.]

3. Turn on VDD_SOC digital voltage supplies.

4. Turn on all VDD_*_0P8 analog, PHY, and PLL supplies.

5. Turn on all remaining 1.8 V supplies. This includes VDD_*_1P8 analog, PHY, PLL supplies, and any 1.8 V NVCC_XXX

I/O supplies.

6. Turn on DDR I/O supplies.

7. Turn on 3.3 V supplies. This includes all 3.3 V NVCC_XXX I/O supplies and VDD_USB_3P3. [This 3.3 V supply step

may be simultaneous with either the 1.8 V or the DDR supplies if desired.]

8. POR_B release (it should be asserted during the entire power-up sequence.)

4.3.2 Power-down sequence

The power-down sequence of i.MX 93 is defined as follows:

• Turn off NVCC_BBSM_1P8 last

• Turn off VDD_SOC after the other (non-BBSM) power rails or at the same time as other (non-BBSM) rails.

• No sequence for other power rails during power down.

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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