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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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IMX93CEC 데이터시트(PDF) 73 Page - NXP Semiconductors |
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IMX93CEC 데이터시트(HTML) 73 Page - NXP Semiconductors |
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73 / 123 page  • A2—Memory generates read data on SCK falling edge and generates read strobe on SCK rising edge Note: In this mode, it is only working under 1.8 V. Table 79. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case A1) (Nominal and Overdrive mode) Symbol Parameter Min Max Unit — Frequency of operation — 200 MHz TSCKD Time from SCK to data valid — — ns TSCKDQS Time from SCK to DQS — — ns TSCKD - TSCKDQS Time delta between TSCKD and TSCKDQS -0.6 0.6 ns Table 80. FlexSPI input timing in SDR mode where FlexSPI n_MCR0[RXCLKSRC] = 0x3 (case A1) (Low drive mode) Symbol Parameter Min Max Unit — Frequency of operation — 133 MHz TSCKD Time from SCK to data valid — — ns TSCKDQS Time from SCK to DQS — — ns TSCKD - TSCKDQS Time delta between TSCKD and TSCKDQS -2 2 ns TSCKD TSCKDQS FLEXSPI_SCLK FLEXSPI_DATA[7:0] FLEXSPI_DQS TSCKD TSCKDQS Figure 44. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (case A1) Note: Timing shown is based on the memory generating read data and read strobe on the SCK rising edge. The FlexSPI controller samples read data on the DQS falling edge. Table 81. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case A2) (Nominal and Overdrive mode) Symbol Parameter Value Unit Min Max — Frequency of operation — 200 MHz TSCKD Time from SCK to data valid — — ns TSCKDQS Time from SCK to DQS — — ns TSCKD - TSCKDQS Time delta between TSCKD and TSCKDQS -0.6 0.6 ns NXP Semiconductors IMX93CEC i.MX 93 Applications Processors Data Sheet for Commercial Products IMX93CEC All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7 — 12 February 2026 Document feedback 73 / 123 |
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