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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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IMX93CEC 데이터시트(PDF) 52 Page - NXP Semiconductors |
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IMX93CEC 데이터시트(HTML) 52 Page - NXP Semiconductors |
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52 / 123 page  SD7 SD1 SD5 SD5 SD6 SCK Output from Strobe Input from uSDHC to eMMC eMMC to uSDHC DAT0 DAT1 DAT7 ... DAT0 DAT1 DAT7 ... SD4 SD4 SD3 SD2 Figure 24. HS400 timing Table 55. HS400 interface timing specification (Nominal and Overdrive mode)[1],[2] ID Parameter Symbols Min Max Unit Card Input Clock SD1 Clock frequency fPP 0 200 MHz SD2 Clock low time tCL 2.2 — ns SD3 Clock high time tCH 2.2 — ns uSDHC Output/Card Inputs DAT (Reference to SCK) SD4 Output skew from Data of edge of SCK tOSkew1 0.45 — ns SD5 Output skew from SCK to Data of edge tOSkew2 0.45 — ns uSDHC Input/Card Outputs DAT (Reference to Strobe) SD6 uSDHC input skew tRQ — 0.45 ns SD7 uSDHC hold skew tRQH — 0.45 ns [1] Input timing assumes an input signal slew rate of 1 ns (20%/80%). [2] Output timing valid for maximum external load CL = 15 pF, which is assumed to be a 8 pF load at the end of a 50 ohm, unterminated, 2-inch microstrip trace on standard FR4 (3.3 pF/inch). For best signal integrity, the series resistance of the transmission line should be matched closely to the RDSON of the I/O pad output driver. Table 56. HS400 interface timing specification (Low drive mode)[1],[2] ID Parameter Symbols Min Max Unit Card Input Clock SD1 Clock frequency fPP 0 133 MHz Table continues on the next page... NXP Semiconductors IMX93CEC i.MX 93 Applications Processors Data Sheet for Commercial Products IMX93CEC All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7 — 12 February 2026 Document feedback 52 / 123 |
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