IMX93CEC datasheet(76/123 Pages) NXP

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TSCKD

TSCKDQS

FLEXSPI_SCLK

FLEXSPI_DATA[7:0]

FLEXSPI_DQS

Figure 47. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3

4.12.9.2 FlexSPI output/write timing

The following sections describe output signal timing for the FlexSPI controller including control signals and data outputs.

4.12.9.2.1 SDR mode

Table 88. FlexSPI output timing in SDR mode (Nominal and Overdrive mode)[1]

Symbol

Parameter

Min

Max

Unit

—

Frequency of operation[2]

—

200

MHz

Tck

SCK clock period

—

TDVO

Output data valid time

—

0.6

TDHO

Output data hold time

-0.6

—

TCSS

Chip select output setup time[3]

(TCSS + 0.5) x

Tck - 0.6

—

TCSH

Chip select output hold time

[3]

(TCSH x Tck) -

0.6

—

[1] These timing specifications are valid only for 1.8 V nominal I/O pad supply voltage. For 3.3 V I/O supply, see Table 89

[2] The maximum frequency supported is 56 MHz when NVCC_xxxx operating at 3.3 V.

[3] TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1 register. See i.MX 93 Applications Processor Reference Manual (IMX93RM) for more details.

Table 89. FlexSPI output timing in SDR mode (Low drive mode)

Symbol

Parameter

Min

Max

Unit

—

Frequency of operation[1]

—

133[2]

MHz

Tck

SCK clock period

7.5

—

TDVO

Output data valid time

—

TDHO

Output data hold time

-2

—

TCSS

Chip select output setup time

(TCSS + 0.5) x

Tck - 2

—

TCSH

Chip select output hold time

[3]

(TCSH x Tck) - 2 —

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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