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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST20-GP1 데이터시트(PDF) 78 Page - STMicroelectronics |
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ST20-GP1 데이터시트(HTML) 78 Page - STMicroelectronics |
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78 / 116 page  ST20-GP1 78/116 ® An overall interrupt request signal (ASC_interrupt) is generated from the OR of the ErrorInterrupt signal and the TxEmpty, TxBufEmpty and RxBufFull signals. Note: the status register cannot be written directly by software. The reset mechanism for the status register is described below. The transmitter interrupt status bits (TxEmpty, TxBufEmpty) are reset when a character is written to the transmitter buffer. The receiver interrupt status bit (RxBufFull) is reset when a character is read from the receive buffer. The error status bits (ParityError, FrameError, OverrunError) are reset when a character is read from the receive buffer. Figure 13.4 ASC status and interrupt registers & & & & & & register register RxBufFullIE TxEmptyIE TxBufEmptyIE ParityErrorIE FrameErrorIE OverrunErrorIE ASCIntEnable ASCStatus OR Receive buffer full interrupt Transmitter empty interrupt Transmit buffer empty interrupt Error interrupt RxBufFull TxEmpty TxBufEmpty ParityError FrameError OverrunError RESERVED RESERVED read 0, write 0 read 0, write 0 |
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