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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST20-GP1 데이터시트(PDF) 6 Page - STMicroelectronics |
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ST20-GP1 데이터시트(HTML) 6 Page - STMicroelectronics |
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6 / 116 page  ST20-GP1 6/116 ® CPU supports the sharing of CPU time between applications without an operating system or executive overhead. The architecture is based on the ST20 CPU core and supporting macrocells developed by SGS- THOMSON Microelectronics. The ST20 micro-core family provides the tools and building blocks to enable the development of highly integrated application specific 32-bit devices at the lowest cost and fastest time to market. The ST20 macrocell library includes the ST20Cx family of 32-bit VL- RISC (variable length reduced instruction set computer) micro-cores, embedded memories, standard peripherals, I/O, controllers and ASICs. The ST20-GP1 uses the ST20 macrocell library to provide the hardware modules required in a GPS system. These include: • DSP hardware • Dual channel UART for serial communications • 6 bits of parallel I/O • Interrupt controller • Real time clock/calendar • Watchdog timer The ST20-GP1 is supported by a range of software and hardware development tools for PC and UNIX hosts including an ANSI-C ST20 software toolset and the ST20 INQUEST window based debugging toolkit. |
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