ST20-GP1 datasheet(90/116 Pages) STMICROELECTRONICS

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ST20-GP1

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15.4.1 Dreq/Dack protocol

In this mode the 2 control pins PlinknotReq (Dreq) and PlinknotAck (Dack) are active low. The

initial (inactive) state of the 2 control wires is high.

Dreq/Dack output

The sequence of events for a Dreq/Dack output is outlined below.

PlinknotReq (Dreq), input to ST20, is taken low by the external ASIC.

The ST20-GP1 asserts the PlinknotAck (Dack) output low. The ASIC can then take

PlinknotReq (Dreq) high.

Following PlinknotAck (Dack) going low, the data in the DMA buffer is applied to the output

pins. PlinknotAck (Dack) is forced high and the output drivers are tristated. The ASIC can

initiate the next transfer.

Dreq/Dack input

The sequence of events for a Dreq/Dack input is outlined below.

PlinknotReq (Dreq), input to ST20, is taken low by the external ASIC.

The ST20-GP1 then asserts the PlinknotAck (Dack) output low.

The external ASIC applies the data to be transferred to the PlinkData0-7 pins. The ASIC

can then return PlinknotReq (Dreq) high at any time.

The data on the input pins is sampled, then PlinknotAck (Dack) is forced high.

Figure 15.1 Dreq/Dack protocol

ST20 Output

PlinknotReq

PlinknotAck

PlinkData0-7

ST20 Input

PlinknotReq

PlinknotAck

PlinkData0-7

(Dreq)

(Dack)

(Dreq)

(Dack)

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