ECP2 datasheet(38/386 Pages) LATTICE

38 / 386 page

2-35

Architecture

Lattice Semiconductor

LatticeECP2/M Family Data Sheet

Figure 2-32. Output and Tristate Block, Top Edge

Tristate Register Block

The tristate register block provides the ability to register tri-state control signals from the core of the device before

they are passed to the sysI/O buffers. The block contains a register for SDR operation and an additional latch for

DDR operation. Figure 2-31 shows the diagram of the Tristate Register Block with the Output Block for the left, right

and bottom edges and Figure 2-32 shows the diagram of the Tristate Register Block with the Output Block for the

top edge.

In SDR mode, ONEG1 feeds one of the ﬂip-ﬂops that then feeds the output. The ﬂip-ﬂop can be conﬁgured a D-

type or latch. In DDR mode, ONEG1 and OPOS1 are fed into registers on the positive edge of the clock. Then in

the next clock the registered OPOS1 is latched. A multiplexer running off the same clock cycle selects the correct

Control Logic Block

The control logic block allows the selection and modiﬁcation of control signals for use in the PIO block. A clock is

selected from one of the clock signals provided from the general purpose routing, one of the edge clocks (ECLK1/

ECLK2) and a DQS signal provided from the programmable DQS pin and provided to the input register block. The

clock can optionally be inverted.

DDR Memory Support

Certain PICs have additional circuitry to allow the implementation of high speed source synchronous and DDR

memory interfaces. The support varies by the edge of the device as detailed below.

Left and Right Edges

PICs on these edges have registered elements that support DDR memory interfaces. One of every 16 PIOs con-

tains a delay element to facilitate the generation of DQS signals. The DQS signal feeds the DQS bus that spans the

set of 16 PIOs. Figure 2-33 shows the assignment of DQS pins in each set of 16 PIOs.

Bottom Edge

PICs on the bottom edge have registered elements that support DDR memory interfaces. One of every 18 PIOs

contains a delay element to facilitate the generation of DQS signals. The DQS signal feeds the DQS bus that spans

the set of 18 PIOs. Figure 2-34 shows the assignment of DQS pins in each set of 18 PIOs.

ONEG1

Note: Simplified version does not show CE and SET/RESET details.

D-Type

/LATCH

ONEG0

ECLK1

ECLK2

CLK1

Tristate Logic

Output Logic

(CLKA)

/LATCH

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