| 전자부품 데이터시트 검색엔진 |
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ECP2 데이터시트(PDF) 97 Page - Lattice Semiconductor |
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ECP2 데이터시트(HTML) 97 Page - Lattice Semiconductor |
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97 / 386 page ![]() 3-45 DC and Switching Characteristics Lattice Semiconductor LatticeECP2/M Family Data Sheet Figure 3-14. sysCONFIG Parallel Port Read Cycle Figure 3-15. sysCONFIG Parallel Port Write Cycle tSUSPI SOSPI Data Setup Time Before CCLK 7 — ns tHSPI SOSPI Data Hold Time After CCLK 2 — ns Timing v.A 0.11 Parameter Min. Max. Units Master Clock Frequency Selected value - 30% Selected value + 30% MHz Duty Cycle 40 60 % Timing v.A 0.11 LatticeECP2/M sysCONFIG Port Timing Specifications (Continued) Over Recommended Operating Conditions Parameter Description Min. Max. Units CCLK CS1N CSN WRITEN BUSY D[0:7] t SUCS t HCS t SUWD t CORD t DCB t HWD t BSCYC t BSCH t BSCL Byte 0 Byte 1 Byte 2 Byte n* *n = last byte of read cycle. CCLK CS1N CSN WRITEN BUSY D[0:7] t SUCS t HCS t SUWD t HCBDI t DCB t HWD t BSCH t BSCL t SUCBDI Byte 0 Byte 1 Byte 2 Byte n* *n = last byte of write cycle. |
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