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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ECP2 데이터시트(PDF) 20 Page - Lattice Semiconductor |
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ECP2 데이터시트(HTML) 20 Page - Lattice Semiconductor |
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20 / 386 page  2-17 Architecture Lattice Semiconductor LatticeECP2/M Family Data Sheet Figure 2-16. Secondary Clock Selection Slice Clock Selection Figure 2-17 shows the clock selections and Figure 2-18 shows the control selections for Slice0 through Slice2. All the primary clocks and the four secondary clocks are routed to this clock selection mux. Other signals can be used as a clock input to the slices via routing. Slice controls are generated from the secondary clocks or other signals connected via routing. If none of the signals are selected for both clock and control then the default value of the mux output is 1. Slice 3 does not have any registers; therefore it does not have the clock or control muxes. Figure 2-17. Slice0 through Slice2 Clock Selection SC0 SC1 SC2 SC3 SC4 SC5 24:1 24:1 24:1 SC6 SC7 24:1 24:1 24:1 24:1 24:1 4 Secondary Clocks/CE/LSR (SC0 to SC3) per Region Clock/Control Secondary Clock Feedlines: 8 PIOs + 16 Routing High Fan-out Data 4 High Fan-out Data Signals (SC4 to SC7) per Region Clock to Slice Primary Clock Secondary Clock Routing Vcc 8 4 12 1 25:1 |
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