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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ECP2 데이터시트(PDF) 91 Page - Lattice Semiconductor |
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ECP2 데이터시트(HTML) 91 Page - Lattice Semiconductor |
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91 / 386 page  3-39 DC and Switching Characteristics Lattice Semiconductor LatticeECP2/M Family Data Sheet Table 3-9. SERDES/PCS Latency Breakdown (Parallel Clock Cycle) Figure 3-12. Transmitter and Receiver Block Diagram Item Description Min. Average Max. Bypass Transmit Data Latency T1 FPGA Bridge Transmit 2 1351 T2 8b10b Encoder 2221 T3 SERDES Bridge Transmit 2221 T4 Serializer 3 2.4 Receive Data Latency R1 Deserializer 3 1.2 R2 SERDES Bridge Receive 2221 R3 Word Alignment 4440 R4 8b10b Decoder 1111 R5 Clock Tolerance Compensation 7 15 23 1 R6 FPGA Bridge Receive 2 1351 1. PCS internal Parallel Clock. This clock rate is same as the rxfullclk in table 8-6. 2. FPGA Bridge latency varies by UP/DOWN Sample FIFO read/write. These numbers were presented for 8bit/10bit interface. The depth of Down Sample/Up Sample FIFO is 4. The earliest read can be done after write clock cycle (1 clock) in Down Sample FIFO. The latest read will be done after the FIFO is full (4 + 1 = 5). For 16b/20b interface, the numbers become doubled. Min = 2, Max = 10. This latency depends on the internal FIFO flag operation. 3. The maximum latency applies to bit0. Bit1 latency = Bit0 latency + 1 UI. Bit2 latency = Bit0 latency + 2 UI. HDOUTPi HDOUTNi Deserializer 1:8/1:10 Polarity Adjust Elastic Buffer FIFO Encoder SERDES PCS BYPASS Transmitter Receiver Recovered Clock FPGA Receive Clock FPGA Receive Data Transmit Data CDR REFCLK HDINPi HDINNi EQ Polarity Adjust Up Sample FIFO SERDES Bridge FPGA Bridge Serializer 8:1/10:1 WA DEC FPGA EBRD Clock Transmit Clock TX PLL REFCLK FPGA Core Down Sample FIFO BYPASS BYPASS BYPASS BYPASS BYPASS BYPASS R1 R2 R3 R4 R5 R6 T1 T2 T3 T4 Transmit Clock |
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