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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ECP2 데이터시트(PDF) 70 Page - Lattice Semiconductor |
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ECP2 데이터시트(HTML) 70 Page - Lattice Semiconductor |
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70 / 386 page  3-18 DC and Switching Characteristics Lattice Semiconductor LatticeECP2/M Family Data Sheet Derating Timing Tables Logic timing provided in the following sections of this data sheet and the ispLEVER design tools are worst case numbers in the operating range. Actual delays at nominal temperature and voltage for best case process, can be much better than the values given in the tables. The ispLEVER design tool can provide logic timing numbers at a particular temperature and voltage. 9x9 Multiplier (All Registers) 420 MHz 36x36 Multiplier (All Registers) 372 MHz 18x18 Multiplier/Accumulate (Input and Output Registers) 295 MHz 18x18 Multiplier-Add/Sub-Sum (All Reg- isters) 420 MHz DSP IP Functions 16-Tap Fully-Parallel FIR Filter 304 MHz 1024-pt, Radix 4, Decimation in Frequency FFT 227 MHz 8x8 Matrix Multiplier 223 MHz Timing v.A 0.11 Register-to-Register Performance (Continued) Function -7 Timing Units |
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