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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ECP2 데이터시트(PDF) 92 Page - Lattice Semiconductor |
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ECP2 데이터시트(HTML) 92 Page - Lattice Semiconductor |
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92 / 386 page  3-40 DC and Switching Characteristics Lattice Semiconductor LatticeECP2/M Family Data Sheet SERDES High Speed Data Receiver (LatticeECP2M Family Only) Table 3-10. Serial Input Data Specifications Input Data Jitter Tolerance A receiver’s ability to tolerate incoming signal jitter is very dependent on jitter type. High speed serial interface stan- dards have recognized the dependency on jitter type and have recently modified specifications to indicate toler- ance levels for different jitter types as they relate to specific protocols (e.g. FC, etc.). Sinusoidal jitter is considered to be a worst case jitter type. Table 3-11. Receiver Total Jitter Tolerance Specification 1 Table 3-12. Periodic Receiver Jitter Tolerance Specification 1 Symbol Description Min. Typ. Max. Units RX-CIDS Stream of nontransitions 1 (CID = Consecutive Identical Digits) @ 10 -12 BER 7 @ 3.125 Gbps 20 @ 1.25 Gbps Bits VRX-DIFF-S Differential input sensitivity 100 — — mV, p-p VRX-IN Input levels 0 — VCCRX + 0.8 V VRX-CM-DC Input common mode range (DC coupled) 0.5 — 1.2 V VRX-CM-AC Input common mode range (AC coupled) 3 0 — 1.5 V TRX-RELOCK CDR re-lock time 2 — — 3000 Bits ZRX-TERM Input termination 50/75 Ohm/High Z — 50 Ohms RLRX-RL Return loss (without package) — 9 — dB 1. This is the number of bits allowed without a transition on the incoming data stream when using DC coupling. 2. This is the typical number of bit times to re-lock to a new phase or frequency within +/- 300 ppm, assuming 8b10b encoded data. 3. AC coupling is used to interface to LVPECL and LVDS. Description Frequency Condition Min. Typ. Max. Units Deterministic 3.125 Gbps 600 mV differential eye — — 0.54 UI, p-p Random 600 mV differential eye — — 0.26 UI, p-p Total 600 mV differential eye — — 0.80 UI, p-p Deterministic 2.5 Gbps 600 mV differential eye — — 0.61 UI, p-p Random 600 mV differential eye — — 0.22 UI, p-p Total 600 mV differential eye — — 0.81 UI, p-p Deterministic 1.25 Gbps 600 mV differential eye — — 0.53 UI, p-p Random 600 mV differential eye — — 0.22 UI, p-p Total 600 mV differential eye — — 0.80 UI, p-p Deterministic 250 Mbps 2 600 mV differential eye — — 0.42 UI, p-p Random 600 mV differential eye — — 0.10 UI, p-p Total 600 mV differential eye — — 0.60 UI, p-p 1. Values are measured with PRBS 2 7-1, all channels operating, FPGA Logic active, I/Os around SERDES pins quiet, voltages are nominal, room temperature. 2. Jitter specification is limited by measurement equipment capability. Description Frequency Condition Min. Typ. Max. Units Periodic 3.125 Gbps 600 mV differential eye — — 0.20 UI, p-p 2.5 Gbps 600 mV differential eye — — 0.22 UI, p-p 1.25 Gbps 600 mV differential eye — — 0.20 UI, p-p 250 Mbps 2 600 mV differential eye — — 0.08 UI, p-p 1. Values are measured with PRBS 2 7-1, all channels operating. 2. Jitter specification is limited by measurement equipment capability. |
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