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Introduction

Lattice Semiconductor

LatticeSC/M Family Data Sheet

1-3

The ispLEVER

® design tool from Lattice allows large complex designs to be efﬁciently implemented using the Lat-

ticeSC family of FPGA devices. Synthesis library support for LatticeSC is available for popular logic synthesis tools.

The ispLEVER tool uses the synthesis tool output along with the constraints from its ﬂoor planning tools to place

and route the design in the LatticeSC device. The ispLEVER tool extracts the timing from the routing and back-

annotates it into the design for timing veriﬁcation.

Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeSC family.

By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design,

increasing their productivity.

Innovative high-performance FPGA architecture, high-speed SERDES with PCS support, sysMEM embedded

memory and high performance I/O are combined in the LatticeSC to provide excellent performance for today’s

leading edge systems designs. Table 1-3 details the performance of several common functions implemented within

the LatticeSC.

Table1-3. Speed Performance for Typical Functions

Functions

Performance (MHz)

32-bit Address Decoder

539

64-bit Address Decoder

517

32:1 Multiplexer

779

64-bit Adder (ripple)

353

32x8 Distributed Single Port (SP) RAM

768

64-bit Counter (up or down counter, non-loadable)

369

True Dual-Port 1024x18 bits

372

FIFO Port A: x36 bits, B: x9 bits

375

1. For additional information, see Typical Building BLock Function Performance table

in this data sheet.

2. Advance information (-7 speed grade).

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