LFSC datasheet(15/237 Pages) LATTICE

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2-11

Architecture

Lattice Semiconductor

LatticeSC/M Family Data Sheet

The setup and hold times of the device can be improved by programming a delay in the feedback or input path of

the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either pro-

grammed during conﬁguration or can be adjusted dynamically.

The Phase Select block can modify the phase of the clock signal if desired. The Spread Spectrum block supports

the modulation of the PLL output frequency. This reduces the peak energy in the fundamental and its harmonics

providing for lower EMI (Electro Magnetic Interference).

The sysCLOCK PLL can be conﬁgured at power-up and then, if desired, reconﬁgured dynamically through the

serial memory interface bus which connects with the on-chip system bus. For example, the user can select inputs,

loop ﬁlters, divider setting, delay settings and phase shift settings. The user can also directly access the SMI bus

through the routing.

The PLL clock input, from pin or routing, feeds into an input divider. There are four sources of feedback signal to the

feedback divider: from the clock net, directly from the voltage controlled oscillator (VCO) output, from the routing or

from an external pin. The signal from the input clock divider and the feedback divider are passed through the pro-

grammable delay before entering the phase frequency detector (PFD) unit. The output of this PFD is used to con-

trol the voltage controlled oscillator. There is a PLL_LOCK signal to indicate that VCO has locked on to the input

clock signal. Figure 2-11 shows the sysCLOCK PLL diagram.

Figure 2-11. PLL Diagram

For more information on the PLL, please see details of additional technical documentation at the end of this data

sheet.

Spread Spectrum Clocking (SSC)

The PLL supports spread spectrum clocking to reduce peak EMI by using “down-spread” modulation. The spread

spectrum operation will vary the output frequency (at 30KHz to 500KHz) in a range that is between its nominal

value, down to a frequency that is a programmable 1%, 2%, or 3% lower than normal.

Digital Locked Loop (DLLs)

In addition to PLLs, the LatticeSC devices have up to 12 DLLs per device. DLLs assist in the management of clocks

and strobes. DLLs are well suited to applications where the clock may be stopped or transferring jitter from input to

output is important, for example forward clocked interfaces. PLLs are good for applications requiring the lowest out-

put jitter or jitter ﬁltering. All DLL outputs are routed as primary/edge clock sources.

The DLL has two independent clock outputs, CLKOP and CLKOS. These outputs can individually select one of the

outputs from the tapped delay line. The CLKOS has optional ﬁne phase shift and divider blocks to allow this output

to be further modiﬁed, if required. The ﬁne phase shift block allows the CLKOS output to phase shifted a further 45,

22.5 or 11.25 degrees relative to its normal position. LOCK output signal is asserted when the DLL is locked. The

ALU HOLD signal setting allows users to freeze the DLL at its current delay setting.

CLKI

CLKFB

CLKOP

CLKOS

VCO/

Loop Filter

Phase

Adjust

PFD

LOCK

Div

Prog

Delay

Prog

Delay

Prog

Delay

Div

Optional Internal Feedback

RSTN

From PFD

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