LFSC datasheet(23/237 Pages) LATTICE

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2-19

Architecture

Lattice Semiconductor

LatticeSC/M Family Data Sheet

Figure 2-20. Input Register Block

DDR/Shift Register Block

Optional

Adaptive

Input

Logic2

• DDR

• DDR + half clock

• DDR + shift x1

• DDR + shift x2

• DDR + shift x43

• Shift x1

• Shift x2

• Shift x43

Routing

INFF

INDD

INCK

IPOS0

CLKDISABLE

CLKENABLE

IPOS1

INEG0

INEG1

LCLKIN (ECLK/SCLK)

HCLKIN (ECLK/SCLK)

Latch

D-Type/

Latch

Delay

Block

LOCK

RUNAIL

(from

PURESPEED

I/O Buffer)

DCNTL[0:8]

(From DLL)

1. UPDATE, Set and Reset not shown for clarity

2. Adaptive input logic is only available in selected PIO

3. By four shift modes utilize DDR/shift register block from paired PIO.

4. CLKDISABLE is used to block the transitions on the DQS pin during post-amble. Its main use is to

disable DQS (typically found in DDR memory interfaces) or other clock signals. It can also be used

to disable any/all input signals to save power.

SDR Register/Latch Block

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