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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LFSC 데이터시트(PDF) 73 Page - Lattice Semiconductor |
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LFSC 데이터시트(HTML) 73 Page - Lattice Semiconductor |
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73 / 237 page  3-29 DC and Switching Characteristics Lattice Semiconductor LatticeSC/M Family Data Sheet JTAG Port Timing Specifications Over Recommended Operating Conditions Figure 3-14. JTAG Port Timing Waveforms Symbol Parameter Min. Max. Units fMAX — 25 MHz tBTCP TCK [BSCAN] Clock Pulse Width 40 — ns tBTCPH TCK [BSCAN] Clock Pulse Width High 50 — mV/ns tBTCPL TCK [BSCAN] Clock Pulse Width Low — 10 ns tBTS TCK [BSCAN] Setup Time — 10 ns tBTH TCK [BSCAN] Hold Time 8 — ns tBTRF TCK [BSCAN] Rise/Fall Time 10 — ns tBTCO TAP Controller Falling Edge of Clock to Valid Output 20 — ns tBTCODIS TAP Controller Falling Edge of Clock to Valid Disable 20 — ns tBTCOEN TAP Controller Falling Edge of Clock to Valid Enable — 10 ns tBTCRS BSCAN Test Capture Register Setup Time 8 — ns tBTCRH BSCAN Test Capture Register Hold Time 10 — ns tBUTCO BSCAN Test Update Register, Falling Edge of Clock to Valid Output —25 ns tBTUODIS BSCAN Test Update Register, Falling Edge of Clock to Valid Disable —25 ns tBTUPOEN BSCAN Test Update Register, Falling Edge of Clock to Valid Enable —25 ns TMS TDI TCK TDO Data to be captured from I/O Data to be driven out to I/O a t a D d il a V a t a D d il a V a t a D d il a V a t a D d il a V Data Captured tBTCPH tBTCPL tBTCOEN tBTCRS tBTUPOEN tBUTCO tBTUODIS tBTCRH tBTCO tBTCODIS tBTS tBTH tBTCP |
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