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LFSC 데이터시트(PDF) 63 Page - Lattice Semiconductor

부품명 LFSC
상세설명  LatticeSC/M Family Data Sheet
PDF  237 Pages
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제조업체  LATTICE [Lattice Semiconductor]
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LFSC 데이터시트(HTML) 63 Page - Lattice Semiconductor

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3-19
DC and Switching Characteristics
Lattice Semiconductor
LatticeSC/M Family Data Sheet
Input Delay Block/AIL Timing
GSR Timing
Internal System Bus Timing
Parameter
Description
Min.
Typ.
Max.
Units
tFDEL
Fine delay time
35
45
80
ps
tCDEL
Coarse delay time
1120
1440
2560
ps
jtAIL
AIL jitter tolerance
1- ((N
1 * tFDEL) / (Clock Period))
UI
1. N = number of fine delays used in a particular AIL setting
Parameter
Description
VCC
-7
-6
-5
Units
Min.
Max.
Min.
Max.
Min.
Max.
tSYNC_GSR_MAX
Maximum operating frequency for
synchronous GSR
1.14V
—
438
—
417
—
398
MHz
0.95V
—
378
—
355
—
337
MHz
tASYNC_GSR_MPW
Minimum pulse width of
asynchronous input
—————
3.3
—
ns
Note: Synchronous GSR goes out of reset in two cycles from the clock edge where the setup time of the FF was met.
Parameter
Description
-7
-6
-5
Units
Min.
Max.
Min.
Max.
Min.
Max.
tHCLK
Maximum operating frequency for internal
system bus HCLK.
—
200
—
200
—
200
MHz
Note: There is no minimum frequency. If HCLK is sourced from the embedded oscillator, the minimum frequency limitation of the oscillator/
divider is about 0.3 MHz. Refer to the osciallator data for missing configuration modes.



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