LFSC datasheet(18/237 Pages) LATTICE

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2-14

Architecture

Lattice Semiconductor

LatticeSC/M Family Data Sheet

Table 2-5. sysMEM Block Conﬁgurations

Bus Size Matching

All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB

word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for

each port varies, this mapping scheme applies to each port.

RAM Initialization and ROM Operation

If desired, the contents of the RAM can be pre-loaded during device conﬁguration. By preloading the RAM block

during the chip conﬁguration cycle and disabling the write controls, the sysMEM block can also be utilized as a

ROM.

Single, Dual and Pseudo-Dual Port Modes

In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory

array. The output data of the memory is optionally registered at the output. A clock is required even in asynchro-

nous read mode.

The EBR memory supports two forms of write behavior for dual port operation:

Normal — data on the output appears only during a read cycle. During a write cycle, the data (at the current

address) does not appear on the output.

Write Through — a copy of the input data appears at the output of the same port.

FIFO Conﬁguration

The FIFO has a write port with Data-in, WCE, WE and WCLK signals. There is a separate read port with Data-out,

RCE, RE and RCLK signals. The FIFO internally generates Almost Full, Full, Almost Empty, and Empty Flags. The

Full and Almost Full ﬂags are registered with WCLK. The Empty and Almost Empty ﬂags are registered with RCLK.

Memory Mode

Conﬁgurations

Single Port

16,384 x 1

8,192 x 2

4,096 x 4

2,048 x 9

1,024 x 18

512 x 36

True Dual Port

16,384 x 1

8,192 x 2

4,096 x 4

2,048 x 9

1,024 x 18

Pseudo Dual Port

16,384 x 1

8,192 x 2

4,096 x 4

2,048 x 9

1,024 x 18

512 x 36

FIFO

16,384 x 1

8,192 x 2

4,096 x 4

2,048 x 9

1,024 x 18

512 x 36

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