H838532H datasheet(355/508 Pages) RENESAS

355 / 508 page

Section 10 Serial Communication Interface

Rev. 1.00 May 30, 2008 Page 335 of 484

REJ09B0436-0100

10.5

Application Notes

The following points should be noted when using SCI3.

(1) Relation between Writes to TDR and Bit TDRE

Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial

transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared to

0 automatically. When SCI3 transfers data from TDR to TSR, bit TDRE is set to 1.

Data can be written to TDR irrespective of the state of bit TDRE, but if new data is written to

TDR while bit TDRE is cleared to 0, the data previously stored in TDR will be lost of it has not

yet been transferred to TSR. Accordingly, to ensure that serial transmission is performed

dependably, you should first check that bit TDRE is set to 1, then write the transmit data to TDR

once only (not two or more times).

(2) Operation when a Number of Receive Errors Occur Simultaneously

If a number of receive errors are detected simultaneously, the status flags in SSR will be set to the

states shown in table 10.14. If an overrun error is detected, data transfer from RSR to RDR will

not be performed, and the receive data will be lost.

Table 10.14 SSR Status Flag States and Receive Data Transfer

SSR Status Flags

Receive Data Transfer

RDRF* OER

FER

PER

RSR

→ RDR

Receive Error Status

Overrun error

Framing error

Parity error

Overrun error + framing error

Overrun error + parity error

Framing error + parity error

Overrun error + framing error + parity error

O : Receive data is transferred from RSR to RDR.

X : Receive data is not transferred from RSR to RDR.

Note:

Bit RDRF retains its state prior to data reception. However, note that if RDR is read

after an overrun error has occurred in a frame because reading of the receive data in

the previous frame was delayed, RDRF will be cleared to 0.

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