| 전자부품 데이터시트 검색엔진 |
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H838532H 데이터시트(PDF) 359 Page - Renesas Technology Corp |
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H838532H 데이터시트(HTML) 359 Page - Renesas Technology Corp |
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359 / 508 page ![]() Section 10 Serial Communication Interface Rev. 1.00 May 30, 2008 Page 339 of 484 REJ09B0436-0100 (8) Transmit and Receive Operations when Making a State Transition Make sure that transmit and receive operations have completely finished before carrying out state transition processing. (9) Switching SCK 3x Function If pin SCK 3x is used as a clock output pin by SCI3 in synchronous mode and is then switched to a general input/output pin (a pin with a different function), the pin outputs a low level signal for half a system clock ( φ) cycle immediately after it is switched. This can be prevented by either of the following methods according to the situation. a. When an SCK 3x function is switched from clock output to non clock-output When stopping data transfer, issue one instruction to clear bits TE and RE to 0 and to set bits CKE1 and CKE0 in SCR3 to 1 and 0, respectively. In this case, bit COM in SMR should be left 1. The above prevents SCK 3x from being used as a general input/output pin. To avoid an intermediate level of voltage from being applied to SCK 3x, the line connected to SCK3x should be pulled up to the V CC level via a resistor, or supplied with output from an external device. b. When an SCK 3x function is switched from clock output to general input/output When stopping data transfer, (i) Issue one instruction to clear bits TE and RE to 0 and to set bits CKE1 and CKE0 in SCR3 to 1 and 0, respectively. (ii) Clear bit COM in SMR to 0 (iii) Clear bits CKE1 and CKE0 in SCR3 to 0 Note that special care is also needed here to avoid an intermediate level of voltage from being applied to SCK 3x. (10) Setup at Subactive or Subsleep Mode At subactive or subsleep mode, SCI3 becomes possible use only at CPU clock is φw/2. |
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