H838532H datasheet(301/508 Pages) RENESAS

301 / 508 page

Section 9 Timers

Rev. 1.00 May 30, 2008 Page 281 of 484

REJ09B0436-0100

(2) 8-bit Event Counter Operation

When bit CH2 is set to 1 in ECCSR, ECH and ECL operate as independent 8-bit event counters.

Figure 9.21 shows an example of the software processing when ECH and ECL are used as 8-bit

event counters.

Start

End

Set CH2 to 1

Clear CUEH, CUEL, CRCH, and CRCL to 0

Clear OVH, OVL to 0

Set CUEH, CUEL, CRCH, and CRCL to 1

Figure 9.21 Example of Software Processing when Using ECH and ECL as 8-Bit Event

Counters

ECH and ECL can be used as 8-bit event counters by carrying out the software processing shown

in the example in figure 9.21. The 8-bit event counter operating clock source is asynchronous

event input from the AEVH pin for ECH, and asynchronous event input from the AEVL pin for

ECL. When the next clock is input after the ECH count value reaches H'FF, ECH overflows, the

OVH flag is set to 1 in ECCSR, the ECH count value returns to H'00, and counting up is restarted.

Similarly, when the next clock is input after the ECL count value reaches H'FF, ECL overflows,

the OVL flag is set to 1 in ECCSR, the ECL count value returns to H'00, and counting up is

restarted. When overflow occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in IENR2 is

1 at this time, an interrupt request is sent to the CPU.

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