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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PCIMX515CJM6C 데이터시트(PDF) 61 Page - Freescale Semiconductor, Inc |
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PCIMX515CJM6C 데이터시트(HTML) 61 Page - Freescale Semiconductor, Inc |
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61 / 184 page  Electrical Characteristics i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 Freescale Semiconductor 61 Preliminary—Subject to Change Without Notice 3.7.1.1 CSPI Master Mode Timing Figure 35 depicts the timing of CSPI in Master mode and Table 52 lists the CSPI Master Mode timing characteristics. Figure 35. CSPI Master Mode Timing Diagram Table 51. CSPI Nomenclature and Routing Module I/O Access eCSPI1 CSPI11, USBH1, and DI1 via IOMUX 1 This set of BGA contacts is labeled CSPI, but is actually an eCSPI channel eCSPI2 NANDF and USBH1 via IOMUX CSPI NANDF, USBH1, SD1, SD2, and GPIO via IOMUX Table 52. CSPI Master Mode Timing Parameters ID Parameter Symbol Min Max Unit CS1 CSPIx_CLK Cycle Time tclk 60 — ns CS2 CSPIx_CLK High or Low Time tSW 6— ns CS3 CSPIx_CLK Rise or Fall tRISE/FALL —— ns CS4 CSPIx_CS_x pulse width tCSLH 15 — ns CS5 CSPIx_CS_x Lead Time (CS setup time) tSCS 5— ns CS6 CSPIx_CS_x Lag Time (CS hold time) tHCS 5— ns CS7 CSPIx_DO Setup Time tSmosi 5— ns CS8 CSPIx_DO Hold Time tHmosi 5— ns CS9 CSPIx_DI Setup Time tSmiso 5— ns CS1 CS7 CS8 CS2 CS2 CS4 CS6 CS5 CS9 CS10 CSPIx_CLK CSPIx_CS_x CSPIx_DO CSPIx_DI CSPIx_DRYN1 CS11 CS3 CS3 |
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