PCIMX515CJM6C datasheet(87/184 Pages) FREESCALE

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Electrical Characteristics

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

3.7.8.7

Asynchronous Interfaces

3.7.8.7.1

Standard Parallel Interfaces

The IPU has four signal generator machines for asynchronous signal. Each machine generates IPU’s

internal control levels (0 or 1) by UP and DOWN are defined in Registers. Each asynchronous pin has a

dynamic connection with one of the signal generators. This connection is redefined again with a new

display access (pixel/component) The IPU can generate control signals according to system 80/68

requirements. The burst length is received as a result from predefined behavior of the internal signal

generator machines.

The access to a display is realized by the following:

•

CS (IPP_CS) chip select

•

WR (IPP_PIN_11) write strobe

•

RD (IPP_PIN_12) read strobe

•

RS (IPP_PIN_13) Register select (A0)

Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 55,

Figure 56, Figure 57, and Figure 58. The timing images correspond to active-low IPP_CS, WR and RD

signals.

Each asynchronous access is defined by an access size parameter. This parameter can be different between

different kinds of accesses. This parameter defines a length of windows, when suitable controls of the

current access are valid. A pause between two different display accesses can be guaranteed by programing

of suitable access sizes. There are no minimal/maximal hold/setup time hard defined by DI. Each control

signal can be switched at any time during access size.

Luma Frequency Response

0-30 MHz

-0.7

0.1

Chroma Frequency Response

0-15 MHz,

YCbCr 422 mode

TBD

Luma Nonlinearity

2.6

Chroma Nonlinearity

2.2

Luma Signal-to-Noise Ratio

0-30 MHz

TBD

Chroma Signal-to-Noise Ratio

0-15 MHz

TBD

1 Guaranteed by design

2 Guaranteed by characterization

3 R

set = 1.05 kOhm

Table 69. TV Encoder Video Performance Specifications (continued)

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