PCIMX515CJM6C datasheet(67/184 Pages) FREESCALE

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Electrical Characteristics

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Figure 40. MII Receive Signal Timing Diagram

3.7.4.2

MII Transmit Signal Timing

The MII transmit signal timing affects the FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and

FEC_TX_CLK signals. The transmitter functions correctly up to a FEC_TX_CLK maximum frequency

of 25 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency

must exceed twice the FEC_TX_CLK frequency. Table 58 lists MII transmit channel timing parameters

and Figure 41 shows MII transmit signal timing diagram for the values listed in Table 58.

Figure 41. MII Transmit Signal Timing Diagram

Table 58. MII Transmit Signal Timing

Num

Characteristic1

1 FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode.

Min

Max

Unit

FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid

—

FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid

—

FEC_TX_CLK pulse width high

35%

65%

FEC_TX_CLK period

FEC_TX_CLK pulse width low

35%

65%

FEC_TX_CLK period

FEC_RX_CLK (input)

FEC_RXD[3:0] (inputs)

FEC_RX_DV

FEC_RX_ER

FEC_TX_CLK (input)

FEC_TXD[3:0] (outputs)

FEC_TX_EN

FEC_TX_ER

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