PCIMX515CJM6C datasheet(84/184 Pages) FREESCALE

84 / 184 page

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Electrical Characteristics

3.7.8.6

Interface to a TV Encoder

The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The timing of

the interface is described in Figure 54.

NOTE

•

The frequency of the clock DISP_CLK is 27 MHz (within 10%)

•

The HSYNC, VSYNC signals are active low.

•

The DRDY signal is shown as active high.

•

The transition to the next row is marked by the negative edge of the

HSYNC signal. It remains low for a single clock cycle

•

The transition to the next field/frame is marked by the negative edge of

the VSYNC signal. It remains low for at least one clock cycles

—

At a transition to an odd field (of the next frame), the negative edges

of VSYNC and HSYNC coincide.

—

At a transition is to an even field (of the same frame), they do not

coincide.

•

The active intervals—during which data is transferred—are marked by

the HSYNC signal being high.

2 Display interface clock down time

3 Display interface clock up time

where CEIL(X) rounds the elements of X to the nearest integers towards infinity.

Tdicd

---T

diclk

ceil

DISP_CLK_DOWN

DI_CLK_PERIOD

-------------------------------------------------------------

⎝⎠

⎛⎞

Tdicu

---T

diclk

ceil

DISP_CLK_UP

DI_CLK_PERIOD

---------------------------------------------------

⎝⎠

⎛⎞

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