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PCIMX515CJM6C 데이터시트(PDF) 83 Page - Freescale Semiconductor, Inc

부품명 PCIMX515CJM6C
상세설명  i.MX51 Applications Processors for Consumer and Industrial Products
PDF  184 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

PCIMX515CJM6C 데이터시트(HTML) 83 Page - Freescale Semiconductor, Inc

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Electrical Characteristics
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1
Freescale Semiconductor
83
Preliminary—Subject to Change Without Notice
The maximal accuracy of UP/DOWN edge of IPP_DATA is
The DISP_CLK_PERIOD, DI_CLK_PERIOD parameters are programmed via registers.
Figure 53 depicts the synchronous display interface timing for access level. The DISP_CLK_DOWN and
DISP_CLK_UP parameters are set via the Register.
Figure 53. Synchronous Display Interface Timing Diagram—Access Level
Table 68. Synchronous Display Interface Timing Characteristics (Access Level)
ID
Parameter
Symbol
Min
Typ1
1The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
These conditions may be chip specific.
Max
Unit
IP16
Display interface clock
low time
Tckl
Tdicd-Tdicu–1.5
Tdicd2–Tdicu3
Tdicd–Tdicu+1.5
ns
IP17
Display interface clock
high time
Tckh
Tdicp–Tdicd+Tdicu–1.5
Tdicp–Tdicd+Tdicu
Tdicp–Tdicd+Tdicu+1.5
ns
IP18
Data setup time
Tdsu
Tdicd–1.5
Tdicu
—
ns
IP19
Data holdup time
Tdhd
Tdicp–Tdicd–1.5
Tdicp–Tdicu
—
ns
IP20o
Control signals offset
times (defines for each
pin)
Tocsu
Tocsu–1.5
Tocsu
Tocsu+1.5
—
IP20
Control signals setup
time to display interface
clock (defines for each
pin)
Tcsu
Tdicd–1.5–Tocsu%Tdicp Tdicu
—
ns
Accuracy
T
diclk
0.75ns
±
=
IP19
IP18
IP20
VSYNC
IP17
IP16
DRDY
HSYNC
other controls
IP20o
local start point
Tdicd
Tdicu
IPP_DISP_CLK
IPP_DATA



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