PCIMX515CJM6C datasheet(127/184 Pages) FREESCALE

127 / 184 page

Electrical Characteristics

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1

Freescale Semiconductor

127

Preliminary—Subject to Change Without Notice

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables

and in the figures.

•

All timings are on Audiomux Pads when SSI is being used for data

transfer.

•

“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

•

The terms WL and BL refer to Word Length (WL) and Byte Length

(BL).

•

For internal Frame Sync operation using external clock, the FS timing is

same as that of Tx Data (for example, during AC97 mode of operation).

Table 92. SSI Receiver Timing with External Clock

Parameter

Min

Max

Unit

External Clock Operation

SS22

(Tx/Rx) CK clock period

81.4

—

SS23

(Tx/Rx) CK clock high period

—

SS24

(Tx/Rx) CK clock rise time

—

6.0

SS25

(Tx/Rx) CK clock low period

—

SS26

(Tx/Rx) CK clock fall time

—

6.0

SS28

(Rx) CK high to FS (bl) high

–10

15.0

SS30

(Rx) CK high to FS (bl) low

—

SS32

(Rx) CK high to FS (wl) high

–10

15.0

SS34

(Rx) CK high to FS (wl) low

—

SS35

(Tx/Rx) External FS rise time

—

6.0

SS36

(Tx/Rx) External FS fall time

—

6.0

SS40

SRXD setup time before (Rx) CK low

—

SS41

SRXD hold time after (Rx) CK low

—

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