AT90SCR100 datasheet(145/433 Pages) ATMEL

145 / 433 page

145

TPR0327AY–SMS–30Jan09

AT90SCR100

Figure 13-35.

Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-

caler (fclk_I/O/8)

13.3.8

8-bit Timer/Counter Register Description

13.3.8.1

TCCR2A – Timer/Counter Control Register A

• Bits 7..6 – COM2A1..0: Compare Match Output A Mode

These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0

bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2A pin

must be set in order to enable the output driver.

When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the

WGM22:0 bit setting. Table 13-17 shows the COM2A1:0 bit functionality when the WGM22:0

bits are set to a normal or CTC mode (non-PWM).

OCF2x

OCR2x

TCNT2

(CTC)

TOP

TOP - 1

TOP

BOTTOM

BOTTOM + 1

clk

I/O

clk

(clk

I/O /8)

Bit

321

$0000B0

COM2A1

COM2A0

COM2B1

COM2B0

WGM21

WGM20

TCCR2A

Read/write

R/W

Initial value

0x00

Table 13-17.

Compare Output Mode, non-PWM Mode

COM2A1

COM2A0

Description

Normal port operation, OC0A disconnected.

Toggle OC2A on Compare Match

Clear OC2A on Compare Match

Set OC2A on Compare Match

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