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AT90SCR100 데이터시트(PDF) 225 Page - ATMEL Corporation

부품명 AT90SCR100
상세설명  8-bit Microcontroller for Smart Card Readers
PDF  433 Pages
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제조업체  ATMEL [ATMEL Corporation]
홈페이지  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT90SCR100 데이터시트(HTML) 225 Page - ATMEL Corporation

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TPR0327AY–SMS–30Jan09
AT90SCR100
17.7.13
UPCFG2X - USB Pipe Configuration Register 2 for Pipe X
Set UPNUM register to point to the relevant Pipe before updating the UPCFG2X register.
• Bits 7..0 - INTFRQ7..0 : Interrupt Pipe Request Frequency
These bits are the maximum value in millisecond of the pulling period for an Interrupt Pipe.
17.7.14
UPSTAX - USB Pipe Status Register for Pipe X
Set UPNUM register to point to the relevant Pipe before using the UPSTAX register.
• Bit 7 - CFGOK : Configure Pipe Memory OK
Set by hardware if the required memory configuration has been successfully performed.
Cleared by hardware when the pipe is disabled. The USB reset and the reset pipe have no effect
on the configuration of the pipe.
• Bit 6 - OVERFI : Overflow
Set by hardware when a the current Pipe has received more data than the maximum length of
the current Pipe. An interrupt is triggered if the FLERRE bit is set.
Shall be cleared by software. Setting by software has no effect.
• Bit 5 - UNDERFI : Underflow
Set by hardware when a transaction underflow occurs in the current isochronous or interrupt
Pipe. The Pipe can’t send the data flow required by the device. A ZLP will be sent instead. An
interrupt is triggered if the FLERRE bit is set.
Shall be cleared by software. Setting by software has no effect.
• Bit 4 - Res : Reserved
The value read from these bits is always 0. Do not set these bits.
• Bits 3..2 - DTSEQ1..0 : Toggle Sequencing Flag
Bit
7
6
5
4
321
0
$00AD
INTFRQ [7..0]
UPCFG2X
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
0x00
This value has no effect for a non-Interrupt Pipe.
Note
Bit
7
6
5
4
321
0
$00AC
CFGOK
OVERFI UNDERFI
-
DTSEQ [1..0]
NBUSYBK [1..0]
UPSTAX
Read/write
R
R/W
R/W
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
0x00
The Host controller has to send a OUT packet, but the bank is empty. A ZLP will
be sent and the UNDERFI bit is set underflow for interrupt Pipe.
Note



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