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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AT90SCR100 데이터시트(PDF) 228 Page - ATMEL Corporation |
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AT90SCR100 데이터시트(HTML) 228 Page - ATMEL Corporation |
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228 / 433 page  228 TPR0327AY–SMS–30Jan09 AT90SCR100 OUT Pipe: Set by hardware when the firmware can write a new data into the Pipe FIFO. Cleared by hardware when the current Pipe FIFO is full. IN Pipe: Set by hardware when the firmware can read a new data into the Pipe FIFO. Cleared by hardware when the current Pipe FIFO is empty. This bit is also cleared by hardware when the RXSTALL or the PERR bit is set • Bit 4 - PERRI : PIPE Error Set by hardware when an error occurs on the current bank of the Pipe. This triggers an interrupt if the PERRE bit is set in the UPIENX register. Refers to the UPERRX register to determine the source of the error. Automatically cleared by hardware when the error source bit is cleared. • Bit 3 - TXSTPI : SETUP Bank ready Set by hardware when the current SETUP bank is free and can be filled. This triggers an inter- rupt if the TXSTPE bit is set in the UPIENX register. Shall be cleared to handshake the interrupt. Setting by software has no effect. • Bit 2 - TXOUTI : OUT Bank ready Set by hardware when the current OUT bank is free and can be filled. This triggers an interrupt if the TXOUTE bit is set in the UPIENX register. Shall be cleared to handshake the interrupt. Setting by software has no effect. • Bit 1 - RXSTALLI / CRCERR : STALL Received / Isochronous CRC Error Set by hardware when a STALL handshake has been received on the current bank of the Pipe. The Pipe is automatically frozen. This triggers an interrupt if the RXSTALLE bit is set in the UPI- ENX register. Shall be cleared to handshake the interrupt. Setting by software has no effect. For Isochronous Pipe: Set by hardware when a CRC error occurs on the current bank of the Pipe. This triggers an inter- rupt if the TXSTPE bit is set in the UPIENX register. Shall be cleared to handshake the interrupt. Setting by software has no effect. • Bit 0 - RXINI : IN Data received Set by hardware when a new USB message is stored in the current bank of the Pipe. This trig- gers an interrupt if the RXINE bit is set in the UPIENX register. Shall be cleared to handshake the interrupt. Setting by software has no effect. |
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