AT90SCR100 datasheet(264/433 Pages) ATMEL

264 / 433 page

264

TPR0327AY–SMS–30Jan09

AT90SCR100

Writing this bit to one enables interrupt on the UDRE0 Flag. A Data Register Empty interrupt will

be generated only if the UDRIE0 bit is written to one, the Global Interrupt Flag in SREG is written

to one and the UDRE0 bit in UCSR0A is set.

• Bit 4 – RXEN0: Receiver Enable 0

Writing this bit to one enables the USART Receiver. The Receiver will override normal port oper-

ation for the RxD0 pin when enabled. Disabling the Receiver will flush the receive buffer

invalidating the FE0, DOR0, and UPE0 Flags.

• Bit 3 – TXEN0: Transmitter Enable 0

Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port

operation for the TxD0 pin when enabled. The disabling of the Transmitter (writing TXENn0to

zero) will not become effective until ongoing and pending transmissions are completed, i.e.,

when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-

mitted. When disabled, the Transmitter will no longer override the TxD0 port

• Bit 2..0 - Reserved Bits in MSPI mode

When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,

these bits must be written to zero when UCSR0B is written.

19.7.4

UCSR0C – USART MSPIM Control and Status Register 0 C

• Bit 7..6 - UMSEL01..0: USART Mode Select

These bits select the mode of operation of the USART as shown in Table 19-3. See “UCSR0C –

USART Control and Status Register C” on page 251 for full description of the normal USART

operation. The MSPIM is enabled when both UMSEL0 bits are set to one. The UDORD0,

UCPHA0, and UCPOL0 can be set in the same write operation where the MSPIM is enabled.

• Bit 5..3 - Reserved Bits in MSPI mode

When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,

these bits must be written to zero when UCSR0C is written.

• Bit 2 - UDORD0: Data Order

When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the

data word is transmitted first. Refer to the Frame Formats section page 4 for details.

Bit

$0000C2

UMSEL01

UMSEL00

UDORD0

UCPHA

UCPOL0

UCSR0C

Read/write

R/W

Initial value

0x06

Table 19-3.

UMSEL0 Bits Settings

UMSEL01

UMSEL00

Mode

Asynchronous USART

Synchronous USART

(Reserved)

Master SPI (MSPIM)

AT90SCR100 데이터시트(PDF) 264 Page - ATMEL Corporation

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