AT90SCR100 datasheet(293/433 Pages) ATMEL

293 / 433 page

293

TPR0327AY–SMS–30Jan09

AT90SCR100

Figure 21-11.

HSSPIDMA Controller Diagram

21.6.1

HSSPIDMACS - HSSPIDMA Control and Status register

This is the control and status register of the HSSPIDMA controller.

• Bit 2 - HSSPIDMAERR : DMA Error Bit

When starting the HSSPIDMA controller, this bit is cleared (zero) by the hardware if the values in

HSSPIDMADH, HSSPIDMADL and HSSPIDMAB registers are suitable for the HSSPIDMA

operation requested.

This bit can also be cleared(zero) by software.

This bit is set (one) by hardware when starting a HSSPIDMA operation and whenever one of

these following cases occurs:

• The base address contained in the registers HSSPIDMADH and HSSPIDMADL is incorrect

(out of the allowed range).

• According to the values of the registers HSSPIDMADH, HSSPIDMADL and HSSPIDMAB

and even if the base address is correct, an address out of the allowed range is going to be

reached.

When a HSSPIDMA operation is started, the AVR is automatically stopped. At the

end of the HSSPIDMA operation, the application software automatically restarts

where it left (actually with the instruction following the launching of the HSSPIDMA

operation). Thus the application software does not need to wait for an interrupt or

to need poll the end of the HSSPIDMA operation.

RAM

Reception DPRAM

Automatic Switch

$100

$10FF

16 bytes

HSSPIDMACS.DMAR

HSSPIDMACS.DMADIR

HSSPIDMACS.DMAERR

DMAD

DMA Controller Diagram

Transmission DPRAM

Automatic Switch

16 bytes

HSSPIDMACS.DMAR

Note

Bit

$0000DC

HSSPIDMAERR

HSSPIDMADIR

HSSPIDMAR

HSSPIDMACS

Read/write

R/W

Initial value

0x00

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