AT90SCR100 datasheet(289/433 Pages) ATMEL

289 / 433 page

289

TPR0327AY–SMS–30Jan09

AT90SCR100

This bit is set (one) when a serial transfer of the number of bytes specified in HSSPICNT is com-

pleted. An interrupt is generated if HSSPIIER.BTDIE is set and global interrupt is enabled.

This bit is cleared by software or by hardware when the HSSPICFG.SPIEN is toggled (enabling

or disabling the HSSPI).

• Bit 5 - RCVOF: Receive Overflow Bit

This bit is set by hardware, when the DPRAM mode is set and the two 16 bytes receive buffers

are full. An interrupt is generated if HSSPIIER.RCVOFIE is set and global interrupt is enabled.

• Bit 4 - NSSRE: NSS Rising Edge

Set (one) by hardware on a rising edge on HSSS

Cleared (zero) by software

• Bit 3 - NSSFE: NSS Falling edge Bit

Set (one) by hardware on a falling edge on HSSS

Cleared (zero) by software

21.5.3

HSSPIIER - HSSPI Interrupt Enable Register

• Bit 7 - TIMEOUTIE: Timeout Interrupt Enable Bit

When set (one), this bit enables the Timeout event as the source of the HSSPI interrupt.

When cleared (zero), this bit disables the Timeout source of the HSSPI interrupt.

• Bit 6 - BTDIE: Byte Transfer Done Interrupt Enable Bit

When set (one), this bit enables the Byte Transfer Done event as the source of the HSSPI

interrupt.

When cleared (zero), this bit disables the Byte Transfer Done source of the HSSPI interrupt.

• Bit 5 - RCVOFIE: Receive Overflow Interrupt Enable Bit

When set (one), this bit enables the Receive Overflow event as the source of the HSSPI

interrupt.

When cleared (zero), this bit disables the Receive Overflow source of the HSSPI interrupt.

• Bit 4 - NSSIE: NSS Interrupt Enable

When set (one), the HSSS interrupt is enabled on falling and rising edges

When cleared (zero), the HSSS interrrupt is disabled

Bit

543

$0000D4

TIMEOUTIE

BTDIE

RCVOFIE

NSSIE

HSSPIIER

Read/write

R/W

Initial value

0x00

AT90SCR100 데이터시트(PDF) 289 Page - ATMEL Corporation

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