ATtiny43U datasheet(118/182 Pages) ATMEL

118 / 182 page

118

8048B–AVR–03/09

ATtiny43U

Figure 16-3. ADC Prescaler

When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion

starts at the following rising edge of the ADC clock cycle.

A normal conversion takes 13 ADC clock cycles, as summarised in Table 16-1 on page 120. The

first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock

cycles in order to initialize the analog circuitry, as shown in Figure 16-4 below.

Figure 16-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)

The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conver-

sion and 13.5 ADC clock cycles after the start of a first conversion. See Figure 16-5. When a

conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In Sin-

gle Conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again,

and a new conversion will be initiated on the first rising ADC clock edge.

7-BIT ADC PRESCALER

ADC CLOCK SOURCE

ADPS0

ADPS1

ADPS2

Reset

ADEN

START

Sign and MSB of Result

LSB of Result

ADC Clock

ADSC

Sample & Hold

ADIF

ADCH

ADCL

Cycle Number

ADEN

212

First Conversion

Conversion

MUX and REFS

Update

MUX and REFS

Update

Conversion

Complete

ATtiny43U 데이터시트(PDF) 118 Page - ATMEL Corporation

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