ATtiny43U datasheet(122/182 Pages) ATMEL

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122

8048B–AVR–03/09

ATtiny43U

conversion completes. The CPU will remain in active mode until a new sleep command is

executed.

Note that the ADC will not automatically be turned off when entering other sleep modes than Idle

mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before enter-

ing such sleep modes to avoid excessive power consumption.

16.8

Analog Input Circuitry

The analog input circuitry for single ended channels is illustrated in Figure 16-8. An analog

source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regard-

less of whether that channel is selected as input for the ADC. When the channel is selected, the

source must drive the S/H capacitor through the series resistance (combined resistance in the

input path).

The ADC is optimized for analog signals with an output impedance of approximately 10k

Ω or

less. If such a source is used, the sampling time will be negligible. If a source with higher imped-

ance is used, the sampling time will depend on how long time the source needs to charge the

S/H capacitor, which can vary widely. With slowly varying signals the user is recommended to

use sources with low impedance, only, since this minimizes the required charge transfer to the

S/H capacitor.

In order to avoid distortion from unpredictable signal convolution, signal components higher than

the Nyquist frequency (f

ADC/2) should not be present. The user is advised to remove high fre-

quency components with a low-pass filter before applying the signals as inputs to the ADC.

Figure 16-8. Analog Input Circuitry

Note:

The capacitor in the figure depicts the total capacitance, including the sample/hold capacitor and

any stray or parasitic capacitance inside the device. The value given is worst case.

16.9

Analog Noise Canceling Techniques

Digital circuitry inside and outside the device generates EMI which might affect the accuracy of

analog measurements. If conversion accuracy is critical, the noise level can be reduced by

applying the following techniques:

• Keep analog signal paths as short as possible.

• Make sure analog tracks run over the analog ground plane.

ADCn

IIH

1..100 k

ohm

CS/H= 14 pF

VCC/2

IIL

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