ATtiny43U datasheet(151/182 Pages) ATMEL

151 / 182 page

151

8048B–AVR–03/09

A: Load Command “0000 1000”.

B: Load Address Low Byte, 0x00.

Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.

Set OE to “1”.

19.7

Serial Programming

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while

RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-

put). See Figure 19-7 below.

Figure 19-7. Serial Programming and Verify

Note:

If clocked by internal oscillator there is no need to connect a clock source to the CLKI pin.

After RESET is set low, the Programming Enable instruction needs to be executed first before

program/erase operations can be executed

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming

operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase

instruction. The Chip Erase operation turns the content of every memory location in both the

Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods

for the serial clock (SCK) input are defined as follows:

Low:> 2 CPU clock cycles for f

ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

High:> 2 CPU clock cycles for f

ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

Table 19-14. Pin Mapping Serial Programming

Symbol

Pins

I/O

Description

MOSI

PB4

Serial Data in

MISO

PB5

Serial Data out

SCK

PB6

Serial Clock

VCC

GND

SCK

MISO

MOSI

RESET/PA7

+1.8 - 5.5V

PB4

PB5

PB6

ATtiny43U 데이터시트(PDF) 151 Page - ATMEL Corporation

ATtiny43U 데이터시트(HTML) 151 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL