HCS12 datasheet(312/452 Pages) FREESCALE

312 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

312

Freescale Semiconductor

The CPU12 can handle up to 128 exception vectors, but the number actually

used varies from device to device, and some vectors are reserved for

Freescale use. Refer to Device User Guide for more information.

Exceptions can be classified by the effect of the X and I interrupt mask bits

on recognition of a pending request.

• Resets, the unimplemented opcode trap, and the SWI instruction are

not affected by the X and I mask bits.

• Interrupt service requests from the XIRQ pin are inhibited when X =

1, but are not affected by the I bit.

• All other interrupts are inhibited when I = 1.

7.3 Exception Priority

A hardware priority hierarchy determines which reset or interrupt is serviced

first when simultaneous requests are made. Six sources are not maskable.

The remaining sources are maskable, and the device integration module

typically can change the relative priorities of maskable interrupts. Refer to

7.5 Interrupts for more detail concerning interrupt priority and servicing.

The priorities of the unmaskable sources are:

1. RESET pin or power-on reset (POR)

2. Clock monitor reset

3. Computer operating properly (COP) watchdog reset

4. Non-maskable interrupt request (XIRQ) signal

5. Unimplemented opcode trap

6. Software interrupt instruction (SWI)

Table 7-1. CPU12 Exception Vector Map(1)

1. See Device User Guide and Interrupt Block Guide for further details

Vector Address

Source

$FFFE–$FFFF

System reset

$FFFC–$FFFD

Clock monitor reset

$FFFA–$FFFB

COP reset

$FFF8–$FFF9

Unimplemented opcode trap

$FFF6–$FFF7

Software interrupt instruction (SWI)

$FFF4–$FFF5

XIRQ signal

$FFF2–$FFF3

IRQ signal

$FF00–$FFF1

Device-specific interrupt sources (HCS12)

$FFC0–$FFF1

Device-specific interrupt sources (M68HC12)

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