HCS12 datasheet(313/452 Pages) FREESCALE

313 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

313

External reset and POR share the highest exception-processing priority,

followed by clock monitor reset, and then the on-chip watchdog reset.

The XIRQ interrupt is pseudo-non-maskable. After reset, the X bit in the

CCR is set, which inhibits all interrupt service requests from the XIRQ pin

until the X bit is cleared. The X bit can be cleared by a program instruction,

but program instructions cannot change X from 0 to 1. Once the X bit is

cleared, interrupt service requests made via the XIRQ pin become

non-maskable.

The unimplemented page 2 opcode trap (TRAP) and the SWI are special

cases. In one sense, these two exceptions have very low priority, because

any enabled interrupt source that is pending prior to the time exception

processing begins will take precedence. However, once the CPU begins

processing a TRAP or SWI, neither can be interrupted. Also, since these are

mutually exclusive instructions, they have no relative priority.

All remaining interrupts are subject to masking via the I bit in the CCR. Most

HCS12 microcontroller units (MCU) have an external IRQ pin, which is

assigned the highest I-bit interrupt priority and an internal periodic real-time

interrupt generator, which has the next highest priority. The other maskable

sources have default priorities that follow the address order of the interrupt

vectors — the higher the address, the higher the priority of the interrupt.

Other maskable interrupts are associated with on-chip peripherals such as

timers or serial ports. On the HCS12, logic in the device integration module

can give one I-masked source priority over other I-masked sources. Refer

to the documentation for the specific HCS12 derivative for more information.

7.4 Resets

M68HC12 devices perform resets with a combination of hardware and

software. Integration module circuitry determines the type of reset that has

occurred, performs basic system configuration, then passes control to the

CPU12. The CPU fetches a vector determined by the type of reset that has

occurred, jumps to the address pointed to by the vector, and begins to

execute code at that address.

The are four possible sources of reset are:

• Power-on reset (POR)

• External reset (RESET pin)

• COP reset

• Clock monitor reset

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