HCS12 datasheet(316/452 Pages) FREESCALE

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S12CPUV2 Reference Manual, Rev. 4.0

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Freescale Semiconductor

generally must be enabled by writing one or more bits in associated control

registers. There may be other interrupt-related control bits and flags, and

there may be specific register read-write sequences associated with

interrupt service. Refer to individual on-chip peripheral descriptions for

details.

7.5.3 Interrupt Recognition

Once enabled, an interrupt request can be recognized at any time after the

I mask bit is cleared. When an interrupt service request is recognized, the

CPU responds at the completion of the instruction being executed. Interrupt

latency varies according to the number of cycles required to complete the

current instruction. Because the fuzzy logic rule evaluation (REV), fuzzy

logic rule evaluation weighted (REVW), and weighted average (WAV)

instructions can take many cycles to complete, they are designed so that

they can be interrupted. Instruction execution resumes when interrupt

execution is complete. When the CPU begins to service an interrupt, the

instruction queue is refilled, a return address is calculated, and then the

return address and the contents of the CPU registers are stacked as shown

in Table 7-2.

After the CCR is stacked, the I bit (and the X bit, if an XIRQ interrupt service

request caused the interrupt) is set to prevent other interrupts from

disrupting the interrupt service routine. Execution continues at the address

pointed to by the vector for the highest-priority interrupt that was pending at

the beginning of the interrupt sequence. At the end of the interrupt service

routine, an RTI instruction restores context from the stacked registers, and

normal program execution resumes.

Table 7-2. Stacking Order on Entry to Interrupts

Memory Location

CPU Registers

SP + 7

RTNH : RTNL

SP + 5

YH : YL

SP + 3

XH : XL

SP + 1

B : A

CCR

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