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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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910GL 데이터시트(PDF) 103 Page - Intel Corporation |
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910GL 데이터시트(HTML) 103 Page - Intel Corporation |
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103 / 426 page  MCHBAR Registers R Datasheet 103 Bit Access & Default Description 6:4 R/W 010b DRAM RAS to CAS Delay (tRCD). This bit controls the number of clocks inserted between a row activate command and a read or write command to that row. 000 = 2 DRAM clocks 001 = 3 DRAM clocks 010 = 4 DRAM clocks 011 = 5 DRAM clocks 100 – 111 = Reserved 3 Reserved 2:0 R/W 010b DRAM RAS Precharge (tRP). This bit controls the number of clocks that are inserted between a row precharge command and an activate command to the same rank. 000 = 2 DRAM clocks 001 = 3 DRAM clocks 010 = 4 DRAM clocks 011 = 5 DRAM clocks 100 – 111 = Reserved |
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