910GL datasheet(105/426 Pages) INTEL

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MCHBAR Registers

Datasheet

105

Bit

Access &

Default

Description

6:4

R/W

000 b

Mode Select (SMS). These bits select the special operational mode of the DRAM

interface. The special modes are intended for initialization at power up.

000 = Post Reset state – When the (G)MCH exits reset (power-up or otherwise),

the mode select field is cleared to “000”.

During any reset sequence, while power is applied and reset is active, the

(G)MCH de-asserts all CKE signals. After internal reset is de-asserted,

CKE signals remain de-asserted until this field is written to a value

different than “000”. On this event, all CKE signals are asserted.

During suspend, (G)MCH internal signal triggers DRAM controller to flush

pending commands and enter all ranks into Self-Refresh mode. As part of

resume sequence, (G)MCH will be reset – which will clear this bit field to

“000” and maintain CKE signals de-asserted. After internal reset is de-

asserted, CKE signals remain de-asserted until this field is written to a

value different than “000”. On this event, all CKE signals are asserted.

During entry to other low power states (C3, S1), (G)MCH internal signal

triggers DRAM controller to flush pending commands and enter all ranks

into Self-Refresh mode. During exit to normal mode, (G)MCH signal

triggers DRAM controller to exit Self-Refresh and resume normal

operation without S/W involvement.

001 = NOP Command Enable – All processor cycles to DRAM result in a NOP

command on the DRAM interface.

010 = All Banks Pre-charge Enable – All processor cycles to DRAM result in an

“all banks precharge” command on the DRAM interface.

011 = Mode Register Set Enable – All processor cycles to DRAM result in a

“mode register” set command on the DRAM interface. Host address lines

are mapped to DRAM address lines in order to specify the command sent.

Host address lines [12:3] are mapped to MA[9:0], and HA[13] is mapped

to MA[11].

101 = Reserved

110 = CBR Refresh Enable – In this mode all processor cycles to DRAM result in

a CBR cycle on the DRAM interface

111 = Normal operation

3:2

Reserved

1:0

DRAM Type (DT). This field is used to select between supported SDRAM types.

This bit is controlled by the MTYPE strap signal.

00 = Reserved

01 = Dual Data Rate (DDR) SDRAM

10 = Second Revision Dual Data Rate (DDR2) SDRAM

11 = Reserved

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