MPC5606S datasheet(64/136 Pages) FREESCALE

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MPC5606S Microcontroller Data Sheet, Rev. 6

Freescale Semiconductor

A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the

junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a

substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the

thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple

estimations and for computational fluid dynamics (CFD) thermal models.

To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization

parameter (



JT) to determine the junction temperature by measuring the temperature at the top center of the package case using

Equation 4:

TJ = TT + (JT x PD)

Eqn. 4

where:

= thermocouple temperature on top of the package (°C)



= thermal characterization parameter (°C/W)

= power dissipation in the package (W)

The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T

thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests

on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from

the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling

effects of the thermocouple wire.

References:

Semiconductor Equipment and Materials International

805 East Middlefield Rd.

Mountain View, CA 94043 USA

(415) 964-5111

MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or

303-397-7956.

JEDEC specifications are available on the WEB at http://www.jedec.org.

3.6

Electromagnetic compatibility (EMC) characteristics

Susceptibility tests are performed on a sample basis during product characterization.

3.6.1

EMC requirements on board

The following practices help minimize noise in applications.

•

Place a 100 nF capacitor between each of the VDD12/VSS12 supply pairs and also between the VDDPLL/VSSPLL pair.

The voltage regulator also requires stability capacitors for these supply pairs.

•

Place a 10

F capacitor on VDDR.

•

Isolate VDDR with ballast emitter to avoid voltage droop during STANDBY mode exit.

•

Enable pad slew rate only as necessary to eliminate I/O noise:

— Enabling slew rate for SMD pads will reduce noise on motors.

— Disabling slew rate for non-SMD pads will reduce noise on non-SMD IOs.

•

Enable PLL modulation (± 2%) for system clock.

•

Place decoupling capacitors for all HV supplies close to the pins.

MPC5606S 데이터시트(PDF) 64 Page - Freescale Semiconductor, Inc

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