MPC5606S datasheet(12/136 Pages) FREESCALE

12 / 136 page

MPC5606S Microcontroller Data Sheet, Rev. 6

Freescale Semiconductor

•

4 slave ports:

— 1 flash port dedicated to the CPU

— Platform SRAM

— QuadSPI serial flash controller

— 1 slave port combining:

–

Flash port dedicated to the Display Control Unit and eDMA module

–

Graphics SRAM

–

Peripheral bridge

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32-bit internal address bus, 32-bit internal data bus

1.6.4

Enhanced Direct Memory Access (eDMA)

The eDMA module is a controller capable of performing complex data movements via 16 programmable channels, with

minimal intervention from the host processor. The hardware micro architecture includes a DMA engine which performs source

and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing

the transfer control descriptors (TCD) for the channels. This implementation is utilized to minimize the overall block size. The

eDMA module provides the following features:

•

16 channels support independent 8-, 16- or 32-bit single value or block transfers

•

Supports variable sized queues and circular queues

•

Source and destination address registers are independently configured to post-increment or remain constant

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Each transfer is initiated by a peripheral, CPU, periodic timer interrupt or eDMA channel request

•

Each DMA channel can optionally send an interrupt request to the CPU on completion of a single value or block

transfer

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DMA transfers possible between system memories, QuadSPI, DSPIs, I2C, ADC, eMIOS and General Purpose I/Os

(GPIOs)

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Programmable DMA Channel Mux allows assignment of any DMA source to any available DMA channel with up to

a total of 64 potential request sources.

1.6.5

Inter-IC communications module (I2C)

The I2C module features the following:

•

Up to four I2C modules supported

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Two-wire bi-directional serial bus for on-board communications

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Compatibility with I2C bus standard

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Multimaster operation

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Software-programmable for one of 256 different serial clock frequencies

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Software-selectable acknowledge bit

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Interrupt-driven, byte-by-byte data transfer

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Arbitration-lost interrupt with automatic mode switching from master to slave

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Calling address identification interrupt

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Start and stop signal generation/detection

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Repeated START signal generation

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Acknowledge bit generation/detection

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Bus-busy detection

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