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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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A32100DX 데이터시트(PDF) 25 Page - Actel Corporation |
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A32100DX 데이터시트(HTML) 25 Page - Actel Corporation |
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25 / 98 page  25 Hi R e l F P GA s AC T 1 T i m i ng C har a c t e r i st i c s (W or s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units Logic Module Propagation Delays tPD1 Single Module 4.7 5.5 ns tPD2 Dual Module Macros 10.8 12.7 ns tCO Sequential Clk to Q 4.7 5.5 ns tGO Latch G to Q 4.7 5.5 ns tRS Flip-Flop (Latch) Reset to Q 4.7 5.5 ns Logic Module Predicted Routing Delays1 tRD1 FO=1 Routing Delay 1.5 1.7 ns tRD2 FO=2 Routing Delay 2.3 2.7 ns tRD3 FO=3 Routing Delay 3.4 4.0 ns tRD4 FO=4 Routing Delay 5.0 5.9 ns tRD8 FO=8 Routing Delay 10.6 12.5 ns Logic Module Sequential Timing 2 tSUD Flip-Flop (Latch) Data Input Setup 8.8 10.4 ns tHD Flip-Flop (Latch) Data Input Hold 0.0 0.0 ns tSUENA Flip-Flop (Latch) Enable Setup 8.8 10.4 ns tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 10.9 12.9 ns tWASYN Flip-Flop (Latch) Asynchronous Pulse Width 10.9 12.9 ns tA Flip-Flop Clock Input Period 23.2 27.3 ns fMAX Flip-Flop (Latch) Clock Frequency 44 37 MHz Input Module Propagation Delays tINYH Pad to Y High 4.9 5.8 ns tINYL Pad to Y Low 4.9 5.8 ns Input Module Predicted Routing Delays1, 3 tIRD1 FO=1 Routing Delay 1.5 1.7 ns tIRD2 FO=2 Routing Delay 2.3 2.7 ns tIRD3 FO=3 Routing Delay 3.4 4.0 ns tIRD4 FO=4 Routing Delay 5.0 5.9 ns tIRD8 FO=8 Routing Delay 10.6 12.5 ns Notes: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 2. Setup times assume fanout of 3. Further derating information can be obtained from the DirectTime Analyzer utility. 3. Optimization techniques may further reduce delays by 0 to 4 ns. |
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