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A32100DX 데이터시트(PDF) 29 Page - Actel Corporation

부품명 A32100DX
상세설명  HiRel FPGAs
PDF  98 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  ACTEL [Actel Corporation]
홈페이지  http://www.actel.com
Logo ACTEL - Actel Corporation

A32100DX 데이터시트(HTML) 29 Page - Actel Corporation

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29
Hi R e l F P GA s
A1 24 0A T i m i n g C har a c t e r i st i c s (continued)
(W or s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
TTL Output Module Timing1
tDLH
Data to Pad High
11.0
13.0
ns
tDHL
Data to Pad Low
13.9
16.4
ns
tENZH
Enable Pad Z to High
12.3
14.4
ns
tENZL
Enable Pad Z to Low
16.1
19.0
ns
tENHZ
Enable Pad High to Z
9.8
11.5
ns
tENLZ
Enable Pad Low to Z
11.5
13.6
ns
tGLH
G to Pad High
12.4
14.6
ns
tGHL
G to Pad Low
15.5
18.2
ns
dTLH
Delta Low to High
0.09
0.11
ns/pF
dTHL
Delta High to Low
0.17
0.20
ns/pF
CMOS Output Module Timing1
tDLH
Data to Pad High
14.0
16.5
ns
tDHL
Data to Pad Low
11.7
13.7
ns
tENZH
Enable Pad Z to High
12.3
14.4
ns
tENZL
Enable Pad Z to Low
16.1
19.0
ns
tENHZ
Enable Pad High to Z
9.8
11.5
ns
tENLZ
Enable Pad Low to Z
11.5
13.6
ns
tGLH
G to Pad High
12.4
14.6
ns
tGHL
G to Pad Low
15.5
18.2
ns
dTLH
Delta Low to High
0.17
0.20
ns/pF
dTHL
Delta High to Low
0.12
0.15
ns/pF
Notes:
1.
Delays based on 50 pF loading.
2.
SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.



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