A32100DX datasheet(33/98 Pages) ACTEL

33 / 98 page

Hi R e l F P GA s

A1 28 0XL Ti m i ng Cha r act e r i s t i cs

(W or s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25°C)

‘–1’ Speed

‘Std’ Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

Logic Module Propagation Delays1

tPD1

Single Module

3.7

4.3

tCO

Sequential Clk to Q

3.7

4.3

tGO

Latch G to Q

3.7

4.3

tRS

Flip-Flop (Latch) Reset to Q

3.7

4.3

Logic Module Predicted Routing Delays2

tRD1

FO=1 Routing Delay

1.7

2.1

tRD2

FO=2 Routing Delay

2.5

3.0

tRD3

FO=3 Routing Delay

3.1

3.6

tRD4

FO=4 Routing Delay

3.7

4.3

tRD8

FO=8 Routing Delay

7.0

8.3

Logic Module Sequential Timing3, 4

tSUD

Flip-Flop (Latch) Data Input Setup

0.4

0.5

tHD

Flip-Flop (Latch) Data Input Hold

0.0

tSUENA

Flip-Flop (Latch) Enable Setup

1.1

1.2

tHENA

Flip-Flop (Latch) Enable Hold

0.0

tWCLKA

Flip-Flop (Latch) Clock Active Pulse

Width

5.3

6.1

tWASYN

Flip-Flop (Latch) Asynchronous Pulse

Width

5.3

6.1

Flip-Flop Clock Input Period

10.7

12.3

tINH

Input Buffer Latch Hold

0.0

tINSU

Input Buffer Latch Setup

0.4

tOUTH

Output Buffer Latch Hold

0.0

tOUTSU

Output Buffer Latch Setup

0.4

fMAX

Flip-Flop (Latch) Clock Frequency

MHz

Notes:

For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.

Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is

based on actual routing delay measurements performed on the device prior to shipment.

Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained

from the DirectTime Analyzer utility.

Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold

timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input

subtracts (adds) to the internal setup (hold) time.

A32100DX 데이터시트(PDF) 33 Page - Actel Corporation

A32100DX 데이터시트(HTML) 33 Page - Actel Corporation

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