| 전자부품 데이터시트 검색엔진 |
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A32100DX 데이터시트(PDF) 35 Page - Actel Corporation |
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A32100DX 데이터시트(HTML) 35 Page - Actel Corporation |
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35 / 98 page ![]() 35 Hi R e l F P GA s A1 28 0XL Ti m i ng Cha r act e r i s t i cs (continued) (W or s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units TTL Output Module Timing1 tDLH Data to Pad High 5.3 6.2 ns tDHL Data to Pad Low 5.7 6.6 ns tENZH Enable Pad Z to High 5.3 6.2 ns tENZL Enable Pad Z to Low 5.8 6.8 ns tENHZ Enable Pad High to Z 7.5 8.9 ns tENLZ Enable Pad Low to Z 7.5 8.9 ns tGLH G to Pad High 5.9 6.9 ns tGHL G to Pad Low 6.6 7.8 ns dTLH Delta Low to High 0.05 0.06 ns/pF dTHL Delta High to Low 0.05 0.09 ns/pF CMOS Output Module Timing1 tDLH Data to Pad High 6.6 7.9 ns tDHL Data to Pad Low 4.7 5.5 ns tENZH Enable Pad Z to High 5.3 6.2 ns tENZL Enable Pad Z to Low 5.8 6.8 ns tENHZ Enable Pad High to Z 7.5 8.9 ns tENLZ Enable Pad Low to Z 7.5 8.9 ns tGLH G to Pad High 5.9 6.9 ns tGHL G to Pad Low 6.6 7.8 ns dTLH Delta Low to High 0.07 0.09 ns/pF dTHL Delta High to Low 0.06 0.09 ns/pF Notes: 1. Delays based on 50 pF loading. 2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at http://www.actel.com/appnotes. |
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