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Z8018233FSC 데이터시트(PDF) 104 Page - Zilog, Inc. |
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Z8018233FSC 데이터시트(HTML) 104 Page - Zilog, Inc. |
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104 / 109 page ![]() 3-104 Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL PRELIMINARY Zilog DS971820600 16550 MIMIC TIMING (Continued) Table K. Interrupt Timing RCVR FIFO Z8L182 Z80182 20 MHz 33 MHz No. Sym Parameter Min Max Min Max 14 tSINT Delay from Stop to Set 2 MPU 2 MPU Interrupt Clock Cycles Clock Cycles 15 tRINT Delay from /HRD (RD RBR or RD LSR) 2 MPU 2 MPU to Reset Interrupt Clock Cycles Clock Cycles Note: These AC parameter values are preliminary and are subject to change without notice. /RD (MPU) TxFIFO HINTR THRE /WR (Host) THR /RD (Host) 11R 17 16 18 Figure 115. Interrupt Timing Transmitter FIFO |
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