Z8018233FSC datasheet(106/109 Pages) ZILOG

106 / 109 page

3-106

Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

PRELIMINARY

Zilog

DS971820600

16550 MIMIC TIMING (Continued)

Table M. RCVR FIFO Bytes Other Than First

Z8L182

Z80182

20 MHz

33 MHz

Sym

Parameter

Min

Max

Min

Max

Units

tRXi

Delay from /HRD

290

RBR to /HRxRDY Inactive

TWxi

Delay from Write to

125

/HTxRDY Inactive

tSXa

Delay From Start to

3 MPU

/HTxRDY Active

Clock Cycles

Clock Generator

The Z80182/Z8L182 ZIP™ uses the Z182 MPUs on-chip

clock generator to supply system clock. The required

clock is easily generated by connection a crystal to the

external terminals (XTAL,EXTAL). The clock output runs at

half the crystal frequency for X2 mode.

Recommended characteristics of the crystal and the values

for the capacitor are as follows (the values will change with

crystal frequency).

Type of crystal:

Fundamental, parallel type crystal

(AT cut is recommended).

Frequency tolerance:

Application dependent.

CL, Load capacitance:

Approximately 22 pF

(acceptable range is 20-30 pF).

RS, equivalent-series resistance:

≤ 60 Ohms

IN=COUT=15~22 pF.

For PHI > 15 MHz (X2 Mode), it is recommended that an

oscillator be used as input to EXTAL.

XTAL

EXTAL

Crystal

Inputs

Note:

These AC parameter values are preliminary and are subject to change without notice.

Figure 117. Circuit Configuration For Crystal

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